The Taiwan Semiconductor Manufacturing Company (TSMC) is reportedly facing difficulties with its next-generation 3-nanometer (nm) semiconductor fabrication process. TSMC is the world's largest contract chip manufacturer and it counts some of the world's largest technology firms in its list of customers. Its 3nm process is set to enter production in the second half of this year according to earlier statements made by management. However, a fresh report from the Taiwanese publication DigiTimes believes that TSMC is facing yield problems with the 3nm process, which can harm the expected production volumes expected from the planned volume production in H2 2022.
TSMC's 3nm Semiconductor Process Might Not Reach Full Volume Production During Second Half Of This Year Believe Rumors
In the semiconductor industry, the early stages of manufacturing involve a company producing large silicon wafers in a limited quality to test its production capabilities. A wafer consists of many individual chips, with the final number dependent on chip sizes. The yield of a chip process refers to the number of chips in a wafer that clear a company's final quality control tests, which involve subjecting them to different voltages and loads that are generally encountered during operation.
DigiTimes reports that chip equipment manufacturers believe TSMC is encountering problems with its 3nm yield. It outlines that TSMC has developed different variants of the 3nm process to account for this difficulty, but despite this, the volume of chips produced via the 3nm node might be insufficient for the company's planned production run during the second half of this year.
TSMC also announced a variant of its first-generation 3nm process which is dubbed as N3. This variant, called N3E will enter production next year, and DigiTimes speculates that the variant is simply there to account for production problems at Taiwan's largest chipmaker.
TSMC's senior vice president of research and development, Dr. Yuh Jier Mii, highlighted during TSMC's technology symposium held in June 2021 that the N3 (3nm) process has received strong industry support and improved performance over the fab's first generation 5nm process. Image: TSMC 2021 Online Technology Symposium/Taiwan Semiconductor Manufacturing Company
Additionally, DigiTimes states that TSMC has introduced another 3nm variant that is dubbed as the N3B. Despite the fab's efforts to keep up with targets, the worrying yield has resulted in TSMC's customers sticking with the company's currently leading edge 5nm chip process.
TSMC's 3nm process uses the FinFET transistor architecture, which is the same one employed by earlier nodes such as the 5nm and 7nm processes. As opposed, the cmpany's distant contract chip manufacturing rival Samsung Foundry intends to use the GAAFET (Gate-All-Around) design for its 3nm process.
Samsung's aggressive production timeline for the 3nm node placed it and TSMC in a race to introduce the advanced process first to the market. However, the Korean company is also facing difficulties with its technologies, some of which are also related to a lack of intellectual property according to reports in the Korean media. Intellectual property, commonly referred to as IP, provides a chipmaker with exclusive technologies that customers can use to differentiate their products in the market.
The alleged yield problems at TSMC should present a mixed bag of news for U.S. chip giant Intel Corporation. The company is reportedly planning to use TSMC's 3nm process for some components, as it brings up its own chip production up to speed. Intel is expected to commence production of its Intel 4 process later this year. This process is thought to lie somewhere in between TSMC's 3nm and 5nm technologies. TSMC's management is confident that its products will be the "most advanced" when launched, while Intel plans to gain a headstart for the future by being the first to acquire the latest chipmaking machines.Continue Reading